FIELD OF THE INVENTION
The present invention relates in general to a multilayer interconnection structure for a semiconductor device, and more particularly to an improvement on a contact hole pattern as well as on a via hole pattern of the multilayer interconnection structure for the semiconductor device.
In a conventional multilayer interconnection structure for a semiconductor device having metal interconnection layers, a contact hole is formed at an intersecting section of the interconnection structure where an upper interconnection layer intersects a lower interconnection layer. In order to provide an enlarged contact area at the intersecting section, each of the interconnection layers is provided with an enlarged portion at its section corresponding to the contact hole for achieving a desired contact overlap.
Hereinbelow, a technique for preparing a known multilayer interconnection structure having a contact hole in conjunction with FIGS. 1 to 5.
With reference to FIG. 1, 2a and 2b, FIG. 1 is a plan view showing an embodiment of a known multilayer interconnection structure for a semiconductor device, and FIGS. 2a and 2b are sectional views taken along the section lines A-A' and B-B' of FIG. 1, respectively.
As shown in these drawings, the known interconnection structure for the semiconductor device comprises a lower interconnection layer 2 and an upper interconnection layer 4 which intersect each other. At the intersecting section of the layers 2 and 4, the wiring structure includes a contact hole 5 for contacting the upper layer 4 with the lower layer 2. Each of the interconnection layers 2 and 4 is provided with an enlarged portion for providing a desired contact margin at the intersecting section. The width of the enlarged portion is larger than the other sections of the interconnection layers 2 and 4.
In order to prepare the contact hole 5, a lower insulating layer 1 is deposited on a semiconductor substrate and, thereafter, the lower interconnection layer 2 is laid on the lower insulating layer 1 by patterning.
The lower interconnection layer 2 is in turn completely coated with an upper insulating layer 3, so that it is insulated from the outside. A part of the upper insulating layer 3 is, thereafter, removed to expose a part of the lower interconnection layer 2 to the outside and to provide a space for the contact hole 5. After the contact hole 5 is formed on the exposed section of the lower interconnection layer 2, the upper interconnection layer 4 is laid on the contact hole 5 such that the upper interconnection layer 4 passes over the contact hole 5 and intersects and contacts with the lower interconnection layer 2.
Turning to FIGS. 3, 4a and 4b, there are shown other embodiments of multilayer interconnection structures of semiconductor devices. These structures are disclosed in U.S. Pat. No. 4,587,549 (date of patent: Jun. 6, 1986, inventors: Yukihiro Ushiku and et al., and assignee: K.K. Toshiba, Japan). FIG. 3 is a plan view of the multilayer interconnection structure of this U.S. patent, and FIGS. 4a and 4b are sectional views taken along the section lines C-C' and D-D' of FIG. 3, respectively. Especially, FIG. 4a shows a section of a multilayer interconnection structure which has a drawback to be overcome by the interconnection structure of FIGS. 3 and 4b.
In a multilayer interconnection structure having the section shown in FIG. 4a, a first insulating layer is deposited on the surface of a semiconductor substrate 5. Thereafter, a lower interconnection layer 6 is laid on the surface of the first insulating layer to be connected to the semiconductor substrate 5 through a plurality of contact holes 8a, 8b, 8c and 8d. A second insulating layer is mounted on the first insulating layer and the lower interconnection layer 6. The interconnection structure also includes an upper interconnection layer 7 which is laid on the second insulating layer such that it intersects the lower interconnection layer 6 and is connected to the layer 6 by means of the contact holes 8b and 8c. In this interconnection structure shown in FIG. 4a, the upper interconnection layer 7 is partially thinner in a stepped portion which is defined by the contact holes, so that the upper interconnection layer 7 has a drawback that it is increased in its resistance and have less reliability. In order to overcome such a drawback, the U.S. Pat. No. 4,587,549 proposes a multilayer interconnection structure in which the contact holes 8b and 8c are placed in a region where the lower and upper interconnection layers 6 and 7 intersect each other, thereby letting the upper interconnection layer 7 have a portion which is not influenced by the profile of the contact holes as shown in the sectional view of FIG. 4b.
With reference to FIG. 5, there is shown in a sectional view still another embodiment of a multilayer interconnection structure for a semiconductor device of the prior art. This structure is disclosed in U.S. Pat. No. 4,656,732 (date of patent: Apr. 14, 1987, inventors: Clarence W. Teng and et al., and assignee: Texas Instruments Incorporated).
The technique disclosed in U.S. Pat. No. 4,656,732 provides an integrated circuit wherein the width of contact holes is narrowed by a sidewall oxide, so that the metal interconnection layer can be patterned to minimum geometry everywhere and does not have to be widened where it runs over a contact hole.
However, the aforementioned embodiments of multilayer interconnection structures for a semiconductor device have the following drawbacks, respectively.
In the known multilayer interconnection structure shown in FIG. 4a, an enlarged portion should be provided at the intersecting section, where the upper interconnection layer 7 intersects the lower interconnection layer 6, in order to prevent a contact misalignment. Thus, this structure has a drawback that there is a limit in minimizing the interval between the interconnection layers 6 and 7 and, as a result, the recent trend of improved integration degree of the semiconductor device can not be achieved in this structure.
In the known structure shown in FIG. 4b and disclosed in U.S. Pat. No. 4,587,549, the upper and lower interconnection layers intersect each other above the contact holes, and the contact hole overlaps no part of the traverse region of the upper interconnection layer in the intersecting section. Thus, this structure somewhat improves the integration degree of the semiconductor device, however, the improvement of the integration degree of this structure is attended with reduction of the contact hole size, thereby introducing a drawback that the contact resistance is increased.
In the same manner, the multilayer interconnection structure disclosed in U.S. Pat. No. 4,656,732 somewhat improves the integration degree of the circuit since the width of the contact holes is narrowed by the sidewall oxide. However, this structure has a drawback caused by the reduction of the contact hole size. That is, the contact hole size of this structure is reduced in accordance with improvement of integration degree and this rapidly increases the contact resistance.